The subject matter of the present invention is a process for the manufacture of a thin-film transistor with a selfaligned grid.
It permits particularly the manufacture of thin-layer semiconductor components which can serve for making active matrices for planar liquid crystal displays, for making photodiode matrices, and in general for the multiplexing of components arrayed in matrix form, as well as for making charge transfer devices (DTC [French] or CCD in English).
The various known techniques for making thin-film transistors, particularly photolithography with mask alignment or evaporation and masking for CdSe semiconductors, lead inevitably to causing the transistor grid to be overlapped by the source and drain of the latter. These overlaps introduce stray capacitances whose relative importance increases as the length of the transistor channel decreases. These capacitances are particularly prejudicial to the operation of thin-layer transistors made in hydrogenated amorphous silicon, because they introduce, among other things, an increase of the response time of the component and an unacceptable DC voltage level when these components are used in liquid crystal display devices.
Recently a new thin-layer transistor manufacturing process has been proposed enabling the transistor grid to be aligned with the drain and source of the latter, and thus to eliminate the overlap capacitances almost entirely. Such a process has been described in an article in IEEE Electron Device Letters, vol. EDL 3, No. 7, July 1982, entitled, "A self-alignment process for amorphous silicon thin film transistors," by T. Kodama.
Unfortunately, this new process is too complex to be used for the mass production of thin-layer transistors. In particular, this process comprises a great number of steps as well as a delicate phase of interfacing control at the level of the layer of hydrogenated amorphous silicon which is harmful to the later operation of the component (poor interface condition, creation of a stray channel, etc.). Otherwise, the transistors obtained by this process are by no means "electrically" coplanar, that is, the channel and the drain and source electrodes of the transistors are not at all in the same plane.